1. Field of Invention
The present invention relates to semiconductor fabrication. More particularly, the present invention relates to a method for fabricating a capacitor in a semiconductor integrated circuit.
2. Description of Related Art
A semiconductor integrated circuit usually needs a capacitor. Particularly, a memory device needs the capacitors for each memory cell to store the binary data, according to the bias level of the capacitors. For a memory device such as dynamic random access memory (DRAM), generally, an array of capacitors on the substrate are storing the binary data by charging or discharging the capacitors. One capacitor acts one bit of memory for storing the binary data "0" or "1" corresponding to the status of capacitor being "charged" or "discharged", respectively. The action of read/write in the DRAM is done through a transfer field effect transistor (TFET), in which a source of the TFET is coupled to a bit line (BL), a drain is coupled to the capacitor and a gate is coupled to a word line (WL). The BL carries a voltage level to charge the capacitor through the TFET, where the TFET is selectively controlled by the WL to be activated or inactivated. Thus a writing action can be done. On the other hand, if one wants to read the binary data having been stored, the BL is switched to a comparator circuit, or a sense amplifier, to check the voltage status of the capacitor for the reading action. Therefore the charges stored in the capacitor is essential to a memory quality in the DRAM
The charges stored in the capacitor depends on the capacitance of the capacitor. The capacitance is determined by the storing area of the storage electrode, the isolating reliability between an upper electrode and a lower electrode of the capacitor, and dielectric constant of dielectric, which has been chosen. To be able to store more data, the density of the capacitors used in the memory device tends to increase. This results in the storage charges would be decreased. If the storage charges can stay high, the affections of noise to the sense amplifier for reading can be effectively reduced and it is not necessary to refresh the voltage level of the capacitor, frequently.
While the integration is increasing, the size of memory cell in a DRAM is reduced, accordingly. As known by one skilled in the art, the reduced size of the capacitor gives a result of lower capacitance. If the capacitance is decreased, the soft error due to the .alpha. particles can happen with higher probability. Therefore, it is desired that a capacitor has a reduced size but can keep sufficient capacitance. In order to achieve this purpose, various capacitor structure designs have been proposed, such as a stacked capacitor. However, an efficient method to fabricate a desired capacitor structure is still under developing. A method to fabricate a stack capacitor has been disclosed in U.S. Pat. No. RE36786. However, the method is still not efficient to have the desired capacitance.